1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, more particularly, to a circuit for testing command or address input in a semiconductor memory apparatus.
2. Related Art
Generally, a semiconductor memory apparatus utilizes boundary scan tests as a data input test for determining a pin and an input buffer that receive data. A plurality of input data is input in one bit unit through the input pin, and then buffered and latched to be transmitted to the inside of the semiconductor memory apparatus. Accordingly, the boundary scan test is utilized to determine whether or not the data has been precisely transmitted up to a latching step.
The semiconductor memory apparatus also utilizes a compress test mode to test the input data and shorten the time required for the test by simultaneously testing a plurality of data bits through a compress test. This method of testing the input data is commonly utilized to determine whether or not an input pin of a data input circuit or a latch circuit is defective since a result of the test can be verified through a data input/output buffer.
However, technical problems exist when the method of testing the input data is applied to an input test of an input signal, such as a command signal or an address signal. Since a pin for verifying a result of the input test is required for the input test of the input signal, a test pin is added in a wafer state, thereby decreasing the yield of a wafer. Even though the test pin was necessary in order to perform a test for the input pin of the input signal or the latch circuit in the wafer state, it is difficulty to easily test the input signal due to the decreased yield. For example, the input circuit of the input signal does not easily provide improved reliability, thereby lowering the productivity of the semiconductor memory apparatus.